1. Field of the Invention
The present invention relates to a pattern forming method of resists used in the manufacturing process of semiconductor devices.
2. Discussion of the Background
Together with the progress of semiconductor technology, high speed and high integration implementations of semiconductor devices, in its turn, semiconductor devices have been improved. Accompanied by this, the pattern wire width formed on a semiconductor substrate has been reduced to submicrons, and a lithography technique required for their production and the performance required for resist materials have become more severely needed.
The light source used in the lithography technique is moving in the direction of short wavelengths from the present ultraviolet rays, KrF excimer rays (248 nm of wavelength), etc. Against this trend, the development of resist materials is also progressing, but it is not easy to form patterns of a lower submicron size to cut 0.5 .mu.m.
As a means to solve this problem, a multilayer resist process has been proposed. The multilayer resist process is to share a role charged to the resist by making it multilayer. That is to say, as the basic method of the multilayer resist process, first, a first resist layer of 2 to 3 .mu.m of thickness is formed on the substrate, the steps on the chip surface are made flat, and the reflected light from the ground is absorbed by this resist layer. By carrying out the patterning by the resist layer of high resolution as the second resist layer thereon, the exposure development can be carried out under ideal conditions separated from the ground, and patterns with good dimensional precision are formed at high resolution.
However, the above-mentioned resist process has technical problems, such as the occurrence of pinholes, the occurrence of cracks and curvature by the stress generated between resist layers of different kinds, sophistication of process, pattern conversion difference at patterning of the lower layer, etc.
As a means to solve the problems of the multilayer resist, there is a process called "DESIRE" ("DESIRE: a novel dry developed resist system", Fedor Coopmans, Bruno Roland, pp 34-pp 39, SPIE Vol. 631, Advances in Resist Technology and Processing III (1986)).
This typical process is shown in process cross sectional views in FIGS. 1(a) to 1(d).
That is to say, a resist layer 2 is coated on the surface of a substrate 1 (FIG. 1 (a)). Next, the exposure is carried out using exposure rays 4 like ultraviolet rays, etc., through a mask 3, and an exposure region 5 is formed in the resist layer 2 (FIG. 1 (b)). Against this exposure region 5, the silicon compound is selectively absorbed, and a silylation layer 6 is formed on the surface of the resist layer (FIG. 1 (c)). In succession, the non-exposure region of the resist layer 2 is eliminated by dry etching such as reactive ion etching, etc., and a pattern with a mask of a silicon oxide film is obtained on the surface (FIG. 1 (d)).
The above is the pattern forming method by the typical silylation process. In this process, since absorbing the silicon compound in the exposure region is carried out in a gas atmosphere, the concentration of the silylation layer 6 is larger in profile, the more the surface is exposed to the gas atmosphere and smaller the more it comes into the film.
Therefore, a silicon oxide film 7 obtained from the silylation layer by the reactive etching is limitedly formed only on the surface of the resist layer 2. Since this silicon oxide film 7 is used as the mask for etching the substrate or for patterning the resist layer 2 of the ground, it is necessary to have an adequate film thickness. However, as described above, in this silylation process, since the silicon oxide film 7 is limitedly formed only on the surface of the resist layer 2 and the concentration of silicon oxide film is not always sufficient, the selectivity of patterning and etching is not good. Thus, there is a problem of reliability.
In the silylation process, the formation of the silicon oxide film is carried out by two steps of the process: exposing the resist layer 2 to the silicon compound gas and the reactive ion etching. As a result, the setting of process conditions was complicated in order to obtain the required silicon oxide film.